1. Field of the Invention
The present invention relates to programming of integrated circuits and, more particularly, to architectures and methods for in-circuit programming (ICP) with processors and flash memory semiconductor devices.
2. Description of Related Art
In-circuit programming (ICP) integrated-circuit structures of the prior art have generally relied upon combinations of mask read only memory (ROM) modules and/or flash memory modules under the direct control of a microprocessor. An ICP structure using both a mask read only memory module and a flash memory module, as disclosed in U.S. Pat. No. 5,901,330 the entire contents of which are incorporated herein by reference, requires a die size large enough of course to contain both the mask read only memory module and the flash memory module. Moreover, as a result of such a programming structure utilizing the mask read only memory to store information such as portions of ICP code, this programming structure can be relatively inflexible for facilitating updating the ICP code.
Other ICP structures, such as disclosed in U.S. Pat. No. 6,151,657 the entire contents of which are incorporated herein by reference, harness a pair of flash memory modules or banks, thus requiring a relatively large die size once again to accommodate the multiple flash memory modules. In the configuration of this patent, both of the flash memory modules are apparently needed for implementing the ICP code update.
Both of the aforementioned architecture types thus employ multiple components and may very well implement programming during manufacturing of the devices which cannot be readily or efficiently updated. Another deficiency in these two types of ICP architectures can be a relatively heavy reliance on a microprocessor for ICP code updating that can for example tax the resources of the microprocessor. A need thus exists in the prior-art for an ICP architecture which can reduce costs by conserving for example die space, and which can improve reliability, efficiency and flexibility.